MathWorks, Microsemi collaborate on integrated FPGA-in-the-loop design workflow
April 19, 2018
News
The integrated workflow includes MathWorks? HDL Coder and HDL Verifier, which allow engineers to automatically generate test benches for VHDL and Verilog to rapidly prototype and verify their designs.
ALISO VIEJO, CA. MathWorks and Microsemi have announced an FPGA-in-the-loop verification workflow for PolarFire and SmartFusion2 FPGA development boards. The integrated workflow includes MathWorks’ HDL Coder and HDL Verifier, which allow engineers to automatically generate test benches for VHDL and Verilog to rapidly prototype and verify their designs.
As part of the collaboration, developers are able to leverage MATLAB and Simulink alongside Microsemi’s Libero SoC Design Suite. The integration allows bugs to be identified earlier in the design cycle.
“With the ever-increasing complexity in algorithm designs, it has become imperative for designers to quickly design and validate their algorithms on real hardware,” says Shakeel Peera, vice president FPGA marketing for Microsemi. “This integrated FPGA-in-the-loop workflow of Microsemi FPGA boards with MathWorks HDL Verifier will allow system engineers and algorithm developers to quickly prototype and implement their MATLAB and Simulink designs on Microsemi FPGA development boards through our Libero SoC Design Suite.”
For more information, visit www.microsemi.com/products/fpga-soc/fpgas and www.mathworks.com/products/hdl-verifier.html.
