Infineon’s HYPERRAM Memory Chip Doubles Bandwidth for Low Pin-Count, High-Performance Solutions

By Tiera Oliver

Assistant Managing Editor

Embedded Computing Design

August 03, 2022

News

Infineon’s HYPERRAM Memory Chip Doubles Bandwidth for Low Pin-Count, High-Performance Solutions

Infineon Technologies AG added HYPERRAM 3.0 to its portfolio of high-bandwidth, low-pin count memory solutions. The device features a new,16-bit extended version of the HyperBus interface that doubles throughput to 800 MBps.

With HYPERRAM 3.0, Infineon offers a portfolio of high-bandwidth memories with low pin-count and low-power. It is ideal for applications requiring expansion RAM memory, including video buffering, factory automation, Artificial Intelligence of Things (AIoT), and automotive vehicle-to-everything (V2X), as well as applications requiring scratch-pad memory for intense mathematical calculations.

“The new HYPERRAM 3.0 memory solutions achieve a far higher throughput-per-pin than existing technologies in the market such as PSRAMs and SDR DRAMs,” said Ramesh Chettuvetty, Senior Director of Applications and Marketing at Infineon’s Automotive Division. “Our low-power features enable better power consumption, without sacrificing throughput, which also makes this memory ideal for industrial and IoT solutions.”

Infineon’s HYPERRAM is a stand-alone PSRAM-based volatile memory that offers a simple and cost-optimized way to add extension memory. The data rates are equivalent to SDR DRAM but with much lower pin-count and lower power requirements. The increased per-pin data throughput of the HyperBus interface makes it possible to use microcontrollers (MCUs) with fewer pins and PCBs with fewer layers. This provides opportunities for lower-complexity and thus cost-optimized designs to support target applications.

Infineon introduced the first generation of HYPERRAM devices supporting the HyperBus interface in 2017. The second generation of HYPERRAM devices were introduced in 2021 and support both the Octal xSPI and HyperBus JEDEC-compliant interfaces with data rates of up to 400 MBps. The third generation of HYPERRAM devices support the new extended HyperBus interface enabling 800 MBps data rates. HYPERRAM devices are available in density range of 64 Mb to 512 Mb. They are AEC-Q100 qualified and support industrial and automotive temperature grades up to 125°C.

HYPERRAM 3.0 products can be ordered now in a BGA-49 package.

For more information, visit: www.infineon.com/HYPERRAM.

Tiera Oliver is the assistant managing editor at Embedded Computing Design. She is responsible for web content editing, product news, and story development. She also manages, edits, and develops content for ECD podcasts, including Embedded Insiders.

She utilizes her expertise in journalism and content management to oversee editorial content, coordinate with editors, and ensure high-quality output across web, print, and multimedia platforms. She manages diverse projects, assists in the production of digital magazines, and hosts company podcasts by conducting in-depth interviews with industry leaders to deliver engaging and insightful discussions.

Tiera attended Northern Arizona University, where she received her bachelor's in journalism and political science. She was also a news reporter for the student-led newspaper, The Lumberjack. 

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