Western Digital Announces New Open Solutions, Including a RISC-V Core

December 06, 2018


Western Digital Announces New Open Solutions, Including a RISC-V Core

RISC-V Core IP Can Be Downloaded and Taken to Manufacture by Anyone in the Community

Western Digital (WD) has been one of the most vocal proponents for the RISC-V instruction set architecture (ISA). The company recently took another step toward “putting its money where its mouth is” when it unveiled plans to release a new open-source RISC-V core, an open standard initiative for cache coherent memory over a network, and an open-source RISC-V instruction set simulator. This announcement was made as part of WD CTO Martin Fink’s Keynote Address at the RISC-V Summit in Santa Clara, CA. This is a follow-on to last year’s WD announcement that the company will produce one billion processor cores per year based on RISC-V.

The target applications for the latest Western Digital offerings would be in the Big Data/Fast Data spaces, another name for the coming (and existing) data-centric applications. The core, dubbed SweRV, two-way superscalar device is a 32-bit, nine- stage pipeline core that allows several instructions to be loaded at one time and execute simultaneously, thereby shortening the time taken to run programs. It’s a compact, in-order core and runs at 4.9 CoreMarks/MHz. With a power-efficient design, it offers clock speeds of up to 1.8GHz on a 28-mm CMOS process technology. The company plans to use the SweRV Core in various internal embedded designs, including flash controllers and SSDs.

In an interesting twist, WD is planning to open source its RISC-V SweRV Core. This means that anyone can download the IP and manufacture a microprocessor. Western Digital claims that open sourcing the core will drive development into other data-centric applications, like IoT Edge devices, secure processing, and industrial controls. This move is similar to the rebent NXP announcement that NXP made, where the company is producing a development board, the Vega, and selling it to the RISC-V community at a subsidized price. Al in an effort to jump-start the RISC-V ecosystem

The second part of the announcement, the open standard initiative for cache coherent memory over a network, is dubbed OmniXtend, and it’s specific to an Ethernet fabric. The architecture provides open standard interfaces for access and data sharing across processors, machine learning accelerators, GPUs, FPGAs and other components. It serves as an open solution for efficiently attaching persistent memory to processors.

The third announcement circles back to the first, in that Western Digital introduced an open-source instruction-set simulator (ISS) that works with its new SweRV core. The ISS, which works wqith the new SweRV offering, simulates the processor’s instruction execution. It allows external events to be modeled, such as interrupts and bus errors, and assures the processor core is functioning properly. WD used the SweRV ISS to simulate and validate the SweRV Core, with more than 10 billion instructions executed.