RISC-V Summit to Feature, AI, Auto, RTOS and Many More Key Topics

October 02, 2024

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It’s almost time for the RISC-V Summit North America again and Embedded Computing Design will be there to bring back all the innovation, execution and application you want to know. Let’s take a quick look at what will be going on in the conference session and a few things that we’re particularly interested in attending.

The RISC-V Summit, North America will take place October 22-23, 2024 at the Santa Clara Convention Center in Santa Clara, California.

According to RISC-V International, the organization supporting and defining the standards for RISC-V IP, RISC-V is “defining the future of open computing by providing unprecedented freedom to innovate.” The groups says that more than 13 billion cores have shipped and are being used in AI/ML, wireless, automotive, data center, space, IoT, embedded and solutions in many more vertical and enterprise markets.

At the upcoming RISC-V Summit, the global RISC-V community will be discussion current technological applications, new innovations and the future of standards, specifications and market growth. Looking ahead at the exhibitors and planned conference sessions, we see a few major themes coming to the forefront. These include:

• Automotive
• RTOS
• AI
• Embedded CPU
• Security/Debug & Test/Verification
• Virtualization/Simulation/Digital Twin
• Edge Computing
• RISC-V Market growth/Ecosystem expansion

The first day will be RISC-V Member Day, where technical and industry working groups meet in person to share updates on the status of various efforts and offer interesting technical guides. The following two days launch the show proper, with a full exhibit hall and conference program.

At the conference, attendees will learn about software, systems, development tools, security, and the latest use cases in key markets. Let’s look at some of the sessions we’re most looking forward to.

Realizing RISC-V Certification, and What it Means for your Verification - Adnan Hamid, Breker Verification Systems

One of the early Monday sessions is looking at the real impacts of trust upon the future of RISC-V. For RISC-V to be successful, industry confidence in the quality of produced cores is critical, driving the mission of the RISC-V International Certification Steering Committee (CSC). It is recognized that a high degree of commercial-grade testing is required, leveraging tests from verification specialists, as well as existing work. The CSC has noted the need for small and large core certification, as well as the SoC components around them.

This presentation will analyze the CSC requirements and detail the types of tests that are likely be required, given the focus on architectural analysis that goes much further than basic ISA compliance. We will discuss the kind of scenarios to be validated, and how this can best be accomplished using the required self-checking content. The certification tests could also form the foundation of a comprehensive microarchitectural verification suite. While this is not the goal of certification, we will demonstrate how this might benefit overall verification.

Member Day Session: Why Do We Need Yocto Project on RISC-V - Challenges and Best Practices - Khem Raj, Comcast

On Monday afternoon, RISC-V members will get to join the conversation about how Yocto is critical to RISC-V in embedded systems. The Yocto project is a widely adopted standard set of tools and infrastructure for building Embedded systems,  ranging from complex systems based on Linux to RTOS and bare-metal applications. It's based on OpenEmbedded build technology which has supported RISC-V the architecture from its early days.

The Yocto project has a layered architecture, which provides a scalable mechanism for adding and customizing new hardware and software support. However, there is a balance required for the best outcome.  Core architecture support in the Core layer provides common policies for RISC-V. The architecture layer (meta-riscv) adds additional RISC-V specific customizations and holds support for many SBCs with RISC-V processors. The Yocto Project has gathered years of experience in deploying into a wide range of products e.g. cars, streaming devices, routers, and cameras to name a few.  It is important to leverage these learnings and benefits for the RISC-V ecosystem. This presentation will address the challenges and gaps we have for RISC-V to become tier 1 supported architecture.

In this talk the speaker will provide an overview of how RISC-V is supported in the Yocto project and adjacent layers. Additionally, we will describe the huge opportunity to get RISC-V supported as core architecture.  RISC-V is a fast developing architecture. An important aspect of this presentation will be how to get involved in OSS development on RISC-V.

Keynote: The Next Computing Megatrends are Enabled by RISC-V - Calista Redmond, CEO, RISC-V International

Over the last decade, the industry standard RISC-V Instruction Set Architecture (ISA) has profoundly changed the computing industry with billions of cores shipped and a growing ecosystem of successful businesses all betting their future on RISC-V, but this is only just the beginning. In this session, Calista Redmond will discuss three ways that RISC-V is disrupting and defining the processor industry in the next decade. The ability to customize and extend RISC-V microprocessor designs will usher in an era of workload-defined silicon, where hardware / software co-design enables faster, more efficient compute, optimized for each application. This will power the deployment of AI in mainstream applications, where the flexibility to customize will accelerate innovation and adoption of AI worldwide. This new era of computing will enable developers, industries, and countries to solve local problems, together with access to a global ecosystem and market. Come and discover the future of computing!

Keynote: RISC-V at NVIDIA: One Architecture, Dozens of Applications, Billons of Processors - Frans Sijstermans, Vice President Multimedia Arch/ASIC, NVIDIA

Nine years ago, NVIDIA selected RISC-V for its embedded microcontrollers. Since then, we developed many processors and software stacks, all based on a common underlying hardware and software architecture. Today, every NVIDIA chip comes with multiple embedded RISC-V microcontrollers, each customized for a specific application. In the presentation, we will discuss our architecture as well as several applications. RISC-V’s rich feature set, configurability, extensibility, and active community are reasons why we stand by our 2015 decision to use RISC-V.

We hope you'll join us at the RISC-V Summit! Click here to register and make sure you send us an email if you want to set up a media briefing!