SiFive Advances Custom Silicon Industry with New Partnerships, Products at 7th RISC-V Workshop
November 28, 2017
Inventors of RISC-V and developers of its first Linux-compatible core wrap up 2017 with upsurge in evaluations of industry's most widely adopted RISC-V IP
SAN MATEO, Calif. – Nov. 28, 2017 – At the 7th RISC-V Workshop today, SiFive, the first fabless provider of customized, open-source-enabled semiconductors, announced a number of new partnerships and products that exemplify the company’s rapid growth over the past year. These announcements provide further proof of SiFive’s leadership in aligning with industry leaders to spur innovation in the plateauing semiconductor industry as well as the company’s ability to meet increased demand for open access to custom silicon. The adoption of SiFive’s RISC-V Core IP continues to grow, with more than 150 evaluation licenses in progress.
SiFive news and activities at the workshop include:
An extended partnership with Microsemi: Microsemi and SiFive formed a strategic partnership to create and market a development board based on SiFive’s RISC-V based Freedom Unleashed 500 (U500) platform and Microsemi’s PolarFire FPGAs. (See related press release, “SiFive and Microsemi Expand Relationship with Strategic Roadmap Alignment and a Linux-Capable, RISC-V Development Board.”)
Membership in GLOBALFOUNDRIES’ FDXcelerator Partner Program: SiFive has joined the GF program that brings together select partners to integrate their products or services into validated, plug-and-play design solutions. This provides GF customers access to SiFive RISC-V Core IP alongside a broad set of quality offerings specific to GF’s 22FDX technology.
OnChip demonstration: SiFive partner OnChip will unveil and demonstrate a suite of IP to support analog peripherals and an always-on power domain, which will be available through the DesignShare program to create mixed-signal RISC-V SoCs.
The news comes on the heels of SiFive’s recent release of the industry’s first RISC-V based Linux core: U54-MC Coreplex IP, a 64-bit, quadcore real-time capable application processor with support for full featured operating systems. The standard U54-MC Coreplex contains four U54 CPUs along with a single E51 CPU, and is the first commercial RISC-V core to include multicore support and cache coherence.
SiFive also forged a string of new partnerships recently including:
-SEGGER Microcontroller: SEGGER in September added support for SiFive’s Coreplex IP to its J-Link debug probe, making it the first commercial debugging tool available for RISC-V cores.
-Lauterbach: In October, Lauterbach partnered with SiFive to bring TRACE32 support for high-performance RISC-V cores, providing multicore debugging on individual hardware threads of SiFive cores, enabling debugging right from the reset vector, which analyzes startup codes and other key functions.
Both products will be available for demos at the 7th RISC-V Workshop.
In addition to new partnerships and products, SiFive launched the DesignShare initiative earlier this year to give any company, inventor or maker the ability to harness the power of custom silicon with little to no upfront risk. Within a few months of its debut, companies including Rambus, Flex Logix, UltraSoC, Analog Bits and other industry leaders have joined SiFive’s DesignShare movement to provide low- or no-cost IP to emerging companies, lowering the initial engineering costs required to bring a custom chip design based on the SiFive Freedom platform to realization.
“From the beginning, SiFive has helped lead the charge in driving the advancement of RISC-V in the market,” said Rick O’Connor, executive director of the non-profit RISC-V Foundation. “Its work in expanding the RISC-V IP catalog has been instrumental in the monumental momentum that RISC-V has achieved over the past two years.”
SiFive’s continued commitment to the industry have led to multiple nominations for awards such as “Start-Up to Watch” by Global Semiconductor Alliance Award and two UBM Annual Creativity in Electronics (ACE) Awards.
“This has been a banner year for SiFive,” said Naveed Sherwani, CEO, SiFive. “The progress we have achieved is a direct result of the market’s overwhelming interest in RISC-V as an alternative to legacy architectures. SiFive’s ability to push the barriers of what’s possible and engage with industry leaders has placed us in a strong position as we look ahead to 2018.”
SiFive is the first fabless provider of customized semiconductors based on the free and open RISC-V instruction set architecture. Founded by RISC-V inventors Yunsup Lee, Andrew Waterman and Krste Asanovic, SiFive democratizes access to custom silicon by helping system designers reduce time-to-market and realize cost savings with customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital and Osage University Partners. For more information, visit www.sifive.com.