The CCIX Consortium (CCIX) released its public availability of the CCIX Base Specification Revision 1.0a v1.0, offering non-consortium members the chance to examine the CCIX Base Specification; they are also releasing a full version of the CCIX Base Specification Revision 1.0a.

The public version of the CCIX Base Specification 1.0a helps non-member companies observe essential benefits of CCIX’s chip-to-chip interconnect and features all of the Base Specification 1.0a chapters with the exception of the CCIX PHY chapter, which remains limited to CCIX Consortium members.

The full version of the CCIX Base Specification 1.0a features specific clarifications in the Transaction layer, Datalink layer, and Reliability and Serviceability (RAS), to help Consortium Members integrate the CCIX Standard.

“As the industry demand for a robust cache-coherent interconnect for processors and devices grows, it is important that system designers understand how CCIX can help them optimize and simplify their heterogeneous systems,” said CCIX’s Chairman, Gaurav Singh. “By providing this public version of the CCIX specification, non-consortium members can identify how our open interconnect enables cache coherency, additional bandwidth and reduced latency across all PCI Express generations and benefits not only their own designs, but the industry as a whole.”  

CCIX Consortium will be appearing at the Flash Memory Summit in Booth #948 from August 6-8 in Santa Clara, CA to explain the CCIX Base Specification 1.0a.

Learn more at www.ccixconsortium.com.