Synopsys and Samsung Collaborate on New Production SoC Tapeout
May 02, 2024
News
Synopsys and Samsung have teamed up to announce that they have successfully accomplished the production tapeout for a Samsung high-performance mobile SoC design, according to an announcement this morning.
This SoC will include flagship CPU and GPU, with reportedly 300MHz higher performance using Synopsys.ai full stack AI-driven EDA suite and a broad portfolio of Synopsys IP on Samsung Foundry’s latest Gate-All-Around (GAA) process technologies.
The companies said in the announcement that this was a close collaboration between them with a goal of delivering exceptional performance, power and area (PPA) for their mutual customers, and create the framework for a new generation of chips with generative AI capabilities on Samsung Foundry advanced process nodes.
"Our longstanding collaboration has delivered leading-edge SoC designs. This is a remarkable milestone to successfully achieve the highest performance, power and area on the most advanced mobile CPU cores and SoC designs in collaboration with Synopsys," said Kijoon Hong, vice president of SLSI at Samsung Electronics. "Not only have we demonstrated that AI-driven solutions can help us achieve PPA targets for even the most advanced GAA process technologies, but through our partnership we have established an ultra-high-productivity design system that is consistently delivering impressive results."
Samsung reportedly set stringent performance and low-power requirements for this SoC, and the combination of the Synopsys.ai EDA suite, Synopsys Fusion Compiler RTL-to-GDSII solution for PPA, and Synopsys DSO.ai was critical to the achievement of those goals.
“The relentless demand for ever-better PPA and energy efficiency in high-performance mobile chips is driving the need for high-performance core-specific EDA optimization across the full stack,” said Shankar Krishnamoorthy, GM, EDA Group, Synopsys. “Our extensive set of PPA-boosting capabilities targeted for CPUs and GPUs across the Synopsys AI-driven EDA suite and IP portfolio enables our mutual customers to successfully design chips with the highest quality-of-results for the most advanced Samsung GAA processes.”
The designers used high-performance core-specific techniques such as design partitioning optimization, multi-source clock tree synthesis (MSCTS), advanced wire optimization to minimize crosstalk, and a virtual-flat hierarchical solution in the Synopsys Fusion Compiler solution to achieve an improvement of 300MHz higher performance than alternative approaches and decrease dynamic power requirements by 10 percent, according to the announcement.
This is yet another example in recent months of the merging of AI, IoT, and Embedded computing capabilities into one horizontal Sensor Fusion application enablement layer. It isn’t likely to be the last, since the three technologies are accelerating rapidly into a merging and into ubiquity across all industrial, consumer, and enterprise verticals.
Ken Briodagh is a writer and editor with two decades of experience under his belt. He is in love with technology and if he had his druthers, he would beta test everything from shoe phones to flying cars. In previous lives, he’s been a short order cook, telemarketer, medical supply technician, mover of the bodies at a funeral home, pirate, poet, partial alliterist, parent, partner and pretender to various thrones. Most of his exploits are either exaggerated or blatantly false.
