System in Package: Better performance, smaller footprint

February 01, 2009


System in Package: Better performance, smaller footprint

SiP technology can achieve greater functionality in a reduced time-to-market window that cannot be accomplished through silicon integration or ASIC de...


Embedded electronics in applications such as missile, ordnance, and aircraft platforms continue to require additional processing and performance power without an increase in electronic component volume. Electronics technology creators can boost performance and capability in less space using a variety of techniques including relatively dense standard Plastic Quad Flat Pack (PQFP), ceramic and plastic Ball Grid Array (BGA), Chip Scale Packaging (CSP), Chip on Board (CoB), and System in Package (SiP) multichip packaging.

Each of these methods has potential advantages and disadvantages. BGA and CSP present issues such as ball pitch reduction, nonlead balls that compromise second-level reliability, narrow temperature capabilities, and obsolescence. CoB also poses drawbacks in the form of high-density interconnects, thermal coefficient of expansion mismatch, and yield loss of expensive complex boards.

Circuit board designers often must combine these techniques into an integrated approach to effectively meet the challenges associated with size, weight, and power requirements. Add to this the need for extended product life cycles, preplanned product improvements, modernization, technology refresh, and operational system development, and the challenges can be overwhelming. Each new generation of platforms changes the dynamics in component selection, requiring greater capacity and performance in the same or smaller footprint.

SiP rises above the rest

SiP offers the most effective solution in terms of both performance and time-to-market requirements. As a functional system assembled in a single package, SiP typically contains two or more dissimilar die. For example, one package may combine a processor, programmable logic device, or FPGA with multiple memory types. These devices will be combined with other components including resistors, capacitors, filters, and voltage regulators. All of these elements are then assembled on an interposer to create an integrated product for the intended application.

The benefits of SiP technology include the ability to achieve greater functionality in a reduced time-to-market window that cannot be accomplished through silicon integration or ASIC development. Other advantages include:

  • Reduced board area, board layers, and costs
  • Decreased weight and routing complexity at the PCB level
  • The ability to incorporate different die geometries, silicon technologies, or chips from different fabs into the same package
  • The ability to take high-speed designs off the PCB and include them in the SiP
  • Product upgradeability using die shrinks in the same package, transparent to the OEM

Reducing the size of digital packages in systems is challenging, especially when processing performance and board space requirements are highly constrained by system architecture. Subsystems such as memory SiP or memory plus FPGA devices can help determine if a system must be redesigned or can adapt to changing requirements.

A well-designed SiP addresses both performance and life-cycle management concerns. Manufacturers work proactively with customers to supply specialty packaging when size and space restrictions are critical. In addition, device, package, and speed grade derivatives are eliminated when die can be provided, thus further reducing obsolescence challenges.

Overcoming space limitations

A recent case study that involved a design challenge for an application-specific board layout illustrates the effectiveness of SiP. The designer had a board area of about 160 cm2. With much of the board area populated by the necessary support circuitry such as passives, connectors, and power supply devices, the approximate space remaining for processor, support logic, and memory device components was less than half the total area.

For this application, each processor required 256 MB of DDR SDRAM. The designer initially considered using ten 512 MB DDR SDRAM in 60 Fine-pitch BGA (FBGA) packages to provide the necessary memory density, with each of the FBGAs measuring 10 mm x 12.5 mm on a 1 mm pitch. These ten devices would have included a total of 600 balls needing to be routed and taken up 1,250 mm2 of PCB real estate. Given the system architecture requirements and limits, there simply was not enough space to fit this many components on the board.

Figure 1



To overcome this challenge, the designer selected two 256 MB 208 BGA DDR SDRAM organized as 32M x 72 memory devices from White Electronic Designs. These two components measured 13 mm x 22 mm each and required just 572 mm2 of board space (more than 50 percent savings over the CSP technique) and 416 balls to be routed (30 percent reduction in I/O routing). Figure 1 shows the board floor plan (the actual layout is modified to protect the security of the design and the actual application). This high-performance, high-reliability SiP memory device fulfilled the performance requirements in the limited area and provided additional benefits including:

  • 100 percent burned-in components for device reliability
  • 100 percent tested to temp range
  • Standard Sn63/37Pb metallurgy balls on a 1.27 mm pitch array for second-level reliability
  • Reduced layers in the PCB design, which helped minimize board cost
  • The ability to upgrade the 256 MB DDR SiP to 512 MB as 64M x 72 or 1 GB as 128M x 72 in the same or smaller footprint, thus satisfying tech refresh or preplanned product improvement needs

This case study demonstrates how engineers facing high digital content and stringent space, weight, and height requirements can use SiP semiconductor packages to optimize board space and achieve performance and density breakthroughs.

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Jack Bogdanski is the director of strategic development at White Electronic Designs, based in Phoenix, Arizona. He has 30 years of experience in the electronics packaging industry designing technologies including SiP multichip packaging, memory and microprocessor devices, flip-chip assembly, bump metallurgies, alternative alloys, and flexible circuits and laminates. Jack holds a BSEE and an MBA from Arizona State University.

White Electronic Designs
[email protected]


Jack Bogdanski (White Electronic Designs)