System-on-Chip (SoC) Design- and Development Considerations ? Part 3
April 03, 2019
Design of a control module based on the Arria 10 SoC for use in a medical application.
Besides obvious selection criteria such as availability, price/performance and footprint, other aspects were also essential for the design process:
The HEITEC development team had very good experience with the vendor-specific tools since the development environment is intuitively usable and mature. The Intel Quartus Prime Software Suite features everything required for Intel SoC FPGA developments. It's a complete development package equipped with a user-friendly user interface and technology that helps with the implementation. The tools available on the market are comprehensive, including an evaluation kit, support for a wide range of protocols, data rates and applications, extensive documentation and ARM-compatible software that leverages the strength of the ARM ecosystem. The software and appropriate tools are down- and upwards compatible. In addition to open source Linux, there are a number of options for operating systems, development tools, IP cores and professional services of partners. By working with existing resources, synergies can be generated and existing experiences can be harnessed, reducing risk, enabling migration and accelerating time to market.
Leading Intel DSP design tools include DSP builders for Intel FPGAs for hardware designs and the SDK for OpenCL for software programmers. The hardened floating point blocks are automatically mapped during the design of the algorithms, using the DSP builders for FPGAs or SDK for OpenCL and instancing floating point data types in the software. For smaller design tasks, individual FPGA IP functions and mega functions are available. Intel Design tools automate the optimization and use of floating point blocks and abstract hardware-centric design challenges such as the conversion to fixed points and knowledge of block topologies, pipelining and time multiplexes.
Apart from ECC and better storage connectivity, the Arria10 SoC was also favored by the usability of the pins in order to create a design for increased safety and to reduce power consumption. Fifty-four programmable I/Os are available for general purposes. To occupy the PLL or clock pins, the Intel Quartus Prime Software is used to set I/O assignments. Special high-speed pins are provided for the data output and input. Other multipurpose pins can be used either as single-end I/O or as external feedback pins; furthermore, the I/O Pins can be used as two one-end clock outputs or as differential clock output. Therefore, the layout possibilities of the I/O pins offer a very high degree of flexibility.
Increased Security and Encryption
For larger and more critical system components, it is important to protect designs from unauthorized copying, reverse engineering, and manipulation. Intel FPGAs take this into account by encrypting their configuration bitstreams with the Advanced POF Encryption Standard (AES), and defining or limiting accessible areas. Secure booting is supported based on Elliptical Curve Digital Signature Authentication (EC DSA) and a clear public key infrastructure. Only code from a known and reliable source is accepted.
The 20-nm FPGAs include additional security features that can be activated by using the standalone Qcrypt tool or Intel Quartus Prime Convert Programming File. Tamper Protection and JTAG security mode can be activated separately in 20-nm FPGAs, JTAG can be disabled or prevented from rereading. Safety with ECC into the cache ensures reliable error detection. Seven generally applicable timers and four watchdog timers are implemented. Various control mechanisms are able to prevent overheating or under-voltage.
Energy Efficiency Through Optimized Power Supply
The SoC includes a power sequencing option to achieve optimized power dissipation. The SmartVoltage ID feature enables the FPGA to operate at the same power with less voltage. Thus, the average power consumption spanning the entire set-up can also be reduced and a higher frequency decoupling can be achieved due to the low inductivity. Programmable power supply technology accelerates speed-critical operations while reducing non-critical ones.
In the finally realized concept, the SoC FPGA, including embedded CPU, is connected to the control board of the application and is running with an Embedded Linux operating system. The motherboard features a Gig-E interface to the GUI PC and data interfaces to all other parts of the system. The sample throughput generated by the GUI PC Gigabit Ethernet interface contains the control information in the form of a command list for the local path, including the settings for pulse energy, pulse rate, desired position and speed of the application. After starting the process by foot switch, the control board executes the instructions completely autonomously and monitors all operations simultaneously. Further, all fault conditions, temperature and voltage of the connected devices as well as the energy level are checked. The latter is done by comparing the set and real values of power supply and frequency. In the event of a fault signal, the system is switched off.
Developing a product with a strong architecture is key to ensuring that system design meets its performance requirements now and in the future. With SoCs for embedded systems, designs stand on solid ground. FPGAs for medium-sized applications result in designs with significant space savings and a good balance of power dissipation, cost and performance. The Arria 10 SoC is such a typical representative.
With Arria 10 SoCs, you can reduce board size while increasing performance by integrating a GHz class processor, FPGA logic, and digital signal processing (DSP) into a single customizable system on a chip. Arria 10 SoCs offer a wide range of FPGA logic densities and the hardened floating point DSP implementation facilitates entirely new possibilities for floating point designs. The devices offer the highest floating point performance, energy efficiency and precision while reducing development time.
FPGAs with hardened floating point DSP blocks offer a capacity of 160 to 1,500 GFLOPS in Midrange Arria 10 building blocks. These peak GFLOPS metrics are calculated based on the same transparent methodology used on CPUs, GPUs and DSPs. This methodology provides designers with a reliable technique for the basic comparison of the peak floating point computing capabilities of building blocks based on very different architectures. With the hardened floating point DSP implementation, FPGAs can now be used in a growing range of data intensive applications such as high performance computing (HPC), radar and medical imaging, allowing for more performance at lower total system costs (total cost of ownership). Based on the gained experience, the HEITEC development team can realize SoC with FPGA functionality for almost any application accordingly.
This is the third installment in a series of three blogs. Click here for Part 1 and Part 2.
Executive VP Electronics HEITEC AG
Roland holds degrees in Electronics and Business Administration and worked in a number of senior management positions within the high-tech industry, including Force Computers, Solectron and Rittal. Since 2010 he has been the Executive Vice President of the Electronics Business Unit of HEITEC AG.