PICMG: Full-Speed Ahead in 2020
March 17, 2020
Engagement among our 130 members continues to increase, resulting in a robust com?munity dedicated to developing and promoting open specifications for embedded computing.
Welcome to the Spring PICMG newsletter. Our organization enters 2020 with significant energy after a productive 2019, with more than 50 companies participating on five committees. Engagement among our 130 members continues to increase, resulting in a robust community dedicated to developing and promoting open specifications for embedded computing. We are on track to ratify multiple new and revised specifications in 2020. To learn more and/or join the new initiatives, please contact PICMG.
COM-HPC Gains Momentum
Over the past year, activity behind the Computer-on-Module High-Performance Computing (COM-HPC) initiative has intensified; the team of 20-plus companies reached significant milestones in 2019, including approving the pinout of the new high-performance COM specification. Now, with adoption of this pinout, all committee members have a solid basis from which to work on standard-compliant carrier board designs that offer interfaces supporting up to 100 GbE and PCIe Gen 4.0 and Gen 5.0, up to eight DIMM sockets, and high-speed processors of more than 200 W on standardized COM-HPC modules. The initial spec should be ratified in the first half of 2020; early spec-compatible products are in the design phase. To accelerate development efforts, the committee formed two subgroups focusing on signal-integrity challenges and defining management software elements of the new specification.
IIoT Efforts Move Forward
Doug Sandy, VP of Technology for PICMG, continues to lead our IIoT initiatives related to the sensor domain. Our aggressive approach to advance IIoT encourages a firewalled, secure network architecture supporting a variety of synchronization methods, plus a uniform data model that scales down to the sensor domain through binary encoding. Two formal technical subcommittees have been created. One is focused on the hardware component of connecting sensors and actuators into the secure network, while the other is defining three key components: a binary sensor data model for IIoT, a Redfish sensor data model/schema, and network architecture specifications. This combination of initiatives will provide plug-and-play interoperability at the sensor domain to the “last foot” of the IIoT network.
CompactPCI Serial Extension Underway
This technical subcommittee, sponsored by EKF, Hartmann, and nVent, has the goal of extending the current CompactPCI Serial specification with an update addressing requirements for modern high-speed applications. The subcommittee will strive for maximum interoperability between the current revision and extension. As the market for CompactPCI Serial continues to grow in industrial automation and transportation, extending the standard will guarantee the future success of that technology.
The committee’s stated goals are to support PCIe Gen4 and Gen5; add Ethernet KR4 support; evaluate USB4; support a redundant system slot like CompactPCI Serial for Space; and recommend a robust “utility connector” with locks or screws.
Defining the Next Generation of MicroTCA
The newly formed committee, sponsored by DESY, ESS, Lodz University of Technology, N.A.T., and nVent, will define the next generation of the MicroTCA specification, to address the ever-increasing demand for power and throughput. New components will expand the modules and sub-parts defined in previous revisions of the standard while full backward compatibility will be maintained for all components related to non-fat-pipes-switching. The team plans to implement additional communication protocols such as 100-Gb Ethernet and PCIe Gen4 and Gen5 while keeping the design flexible enough to allow for future developments.
The committee’s goals are to support PCI Gen5; increase power per slot to 160 or 240 W with a potential additional and optional AMC power plug and PM plug; overcome the 80-W limitation for AMCs in current systems at full backward compatibility; overcome the 40-Gbps limitation for fat-pipe bandwidth; completely separate the existing 12-V payload from new optional payload power; and improve cooling. The committee will also work to optimize backplane layout and define routing guidelines, achieve physical separation of base MCH, and fat-pipe switching.
I encourage you to learn more about these ongoing efforts and join PICMG to participate.