AccelerComm announced the release of its Channel Coding software with the Zynq UltraScale+™ RFSoC devices from Xilinx.

Per the company, its reference kit is designed to reduce time to market for 5G NR-compliant FPGA-based solutions. This is because it provides a software interface based on the BBDEV api from the Data Plane Development Kit (DPDK).

The board, which uses the ZU21DR from Xilinx, enables designer to accelerate their RFSoC-based applications.

“For high data rate applications such as 5G, transmission reliability is a key success factor in the quality of the overall system, making a high-performance SD-FEC a major building block in enabling these systems to function under non-ideal environments,” said vice president of marketing, Wired & Wireless Group at Xilinx Dan Mansur, in a press release. “AccelerComm’s channel coding IP is an important addition to the Zynq UltraScale+ RFSoC portfolio. This collaboration will help network equipment manufacturers get to market faster and deliver all-important latency and power consumption improvements in 5G networks.”

The LDPC IP from AccelerComm assists with error correction and addresses the challenges in 5G networks. It’s fully compliant with 3GPP NR standards for PDSCH, PUSCH, and further supports uncoded and enconded block sizes.

For more information, visit www.accelercomm.com