ADC Decimation: Unlocking RF Potential with Downconverters

By Chase Wood

Applications Engineer, high-speed data converters

Texas Instruments

February 29, 2024


ADC Decimation: Unlocking RF Potential with Downconverters

In part 1, I discussed the challenges that system designers face and the promises of decimation in enhancing system efficiency and reducing complexity. In the second installment of this three-part series, I’ll look at the nuances of decimation, revealing the advantages as a result of this process.

This is the second part of a series on ADC Decimation. Click here for part one.

First, let’s review some common features found in radio frequency (RF) sampling converters and understand how these features lay the groundwork for decimation, from multiband outputs to fast frequency hopping. These features enhance system efficiency, reduce complexity, and open doors to new possibilities in existing RF applications.

Common RF data converter features

The term “RF sampling converter” refers to any data converter intended for or targeted toward RF applications. These RF sampling converters commonly integrate various digital features, including a programmable numerically controlled oscillator (NCO), decimation filters and a mixer in the digital core of the analog-to-digital converter (ADC). Integration of these features enables ease of use and flexibility in the down conversion of narrowband RF signals.

Additionally, these RF sampling converters often incorporate another notable feature: multiple digital downconverter (DDC) cores per ADC input. The use of multiple DDC cores for a common input enables a multiband output, with each DDC containing its own unique NCO(s). This functionality reduces the number of receiver paths in any signal chain, improving a system’s overall size, weight, power and cost by eliminating some traditional receiver components.

Another increasinFig 1: Phase-continuous (top) vs. phase-coherent (bottom) NCO operationgly popular feature is fast frequency hopping, allowing the ADC to quickly swap between pre-programmed NCO frequencies in less than 1µs. In devices without this function, the NCO change is limited by the serial interface and the time required to rewrite the (often large) NCO frequency word registers. Some of these RF sampling ADCs offer a coherent NCO, enabling phase-coherent NCO frequency swapping rather than traditional phase-continuous NCO swapping, as shown in Figure 1. If the ADC operates with NCO1 set to an arbitrary frequency (f1) and then changed to a different arbitrary frequency (f2), whenever the NCO1 value returns to the f1 frequency there is no phase variation between the NCO. This is a very important feature, because it means that you no longer need a field-programmable gate array (FPGA) to maintain an NCO counter before issuing the NCO frequency change on a large prime factor.

Converter decimation and a bit of math

Most data converters implementing on-chip decimation allow for two different types of decimation: complex decimation and real decimation. Let’s explore these in detail, beginning with real decimation.

Fig 2: Decimation-by-eight frequency band regions (normalized)In the real decimation modes, you use the process described in “ADC Decimation: Addressing High Data-Throughput Challenges” to simply filter the signals to within the first Nyquist region. In complex decimation modes, you use an NCO for downconversion of the incoming RF signal to baseband before the decimation process. The NCO is internal to the ADC and programmed through the serial interface. This digital NCO replaces the local oscillator in typical analog downconverter stages while also enabling dynamic configuration of the RF signal chain, all from within the ADC itself.

Complex decimation is more popular than real decimation, given that RF carrier frequencies are typically far from DC. After the RF signal is downconverted, the digital decimation filters come into play, addressing unwanted tones and aliasing, leaving only the band of interest at baseband for the upcoming decimator stage. Because ideal filters are unrealizable, there is an additional reduction in bandwidth from the filter’s rolloff, leaving around 80 percent (typically) of the bandwidth as useful. As described in part 1, the tones within any transition band experience some level of attenuation, so it’s best to avoid operating near the transition band to prevent nonlinearity and heavy signal attenuation.

Upon successful programming into a decimation mode, the ADC handles all finite impulse response (FIR) filter settings, including filter depth and the definition of FIR tap coefficients, which relieves system designers from theFig 3: Decimation-by-16 frequency band regions (normalized) chore of calculating the latter. Interestingly, because higher-order digital FIR filters have sharper rolloff and improved stop-band attenuation, the ADC filter performance follows suit. In these devices, the number of taps in the FIR filter is directly related to the decimation factor. For example, if the decimation factor increases by a factor of 2 from decimation by eight (as shown in Figure 2) to decimation by 16 (as shown in Figure 3), the FIR filter sharpness increases by a factor of 2 and the corner frequency (fc) reduces to fc/2.

Higher-order FIR filter processing comes at the cost of increased power consumption, however. As a result, 80 percent bandwidth is a common value in RF sampling converters, providing a decent balance between filter performance and power consumption. With proper frequency planning, a 20 percent bandwidth reduction is not a cause for concern for most applications. Equation 1 calculates the useful bandwidth for a complex decimation mode:


For instance, if operating at 2GSPS, a decimate-by-eight filter is useful when the input signal of interest falls within a 200MHz band.

Complementary to complex decimation, a real decimation mode does not use any digital mixer, nor an NCO. Equation 2 calculates the useful bandwidth for real decimation. Note that unlike complex decimation, the pass band is only half the size, as only the real portion of the complex digital FIR filter is used.

Using Equation 2, if operating at the same 2GSPS, a decimation-by-eight filter is useful to implement for input signals at or below 100MHz.

Ultimately, real decimation is useful as a means of data-rate reduction for applications at or below 40 percent of the first Nyquist zone. I recommend choosing decimation bypass mode (referring to the decimation block being bypassed) or a complex decimation mode for applications with input frequencies above 40 percent of fNYQ1.

Converter decimation benefits

What else can decimation do for you? I know what you're thinking – “This is great and all, but I’m not interested in sampling signals beyond FS2. Is there any benefit of using decimation if my signal is in the first Nyquist zone?” The answer is absolutely! There are many benefits that are a direct result of decimation.

The first (and arguably most useful) benefit is a reduction in the ADC output data rate, occurring after the sampling of the input signal at the full sampling rate. In other words, you can maintain high sampling rates and converter performance while gaining additional flexibility in frequency planning options – truly a system engineer’s dream.

Another wonderful benefit of decimation is that digital filtering filters out wideband noise. This reduction of noise in the spectrum improves the dynamic range (in terms of the spurious free dynamic range) by attenuating spurs to the attenuation specification of the FIR filter while pushing higher-order harmonics out of band with proper frequency planning. Decimating by any factor greater than 1 introduces processing gain, further improving the signal-to-noise ratio (SNR) as a result of the reduction in bandwidth, and therefore a reduction in wideband noise. As shown in Equation 3, the ideal processing gain is simply the improvement in SNR caused by a reduction of total noise within the ADC, which you can think of in terms of the decimation factor as a result of wideband noise reduction:



Ideally, SNR should improve by 10xlog_10 (M) in any decimation mode. For example, if decimating by two, the SNR should improve by 3.01dB, since half the noise is eliminated while the signal of interest remains in band.

Remember, the low-pass decimation filter is not ideal in hardware implementations; filter rolloff is thus an additional consideration. Given the high flexibility in frequency-planning options with decimation-enabled ADCs, you can actually consider the decimation filter’s transition band as advantageous through additional noise reductions or by increasing the processing gain, as shown in Equation 4:



Most RF sampling converters use a JESD204 interface with large throughput, often in excess of 80Gbps, to transmit data to an FPGA. After the implementation of decimation and the reduction in the sheer volume of output data, you can configure the JESD204 interface in a variety of ways, giving you more flexibility. For instance, if using an eight-lane JESD204B or JESD204C device, you may choose to maintain the eight physical data lanes because your routing constraints are not as important as maintaining a low output data rate or supporting wideband operational modes (or both). In a different application, however, you may prefer to route as few lanes as necessary, having each lane run at a faster data rate. These decisions are now available for you, increasing flexibility with existing design constraints, such as an FPGA with a limited transceiver speed or a limited number of input/output pins.

In recent years, lower-sample-rate devices, often implementing a complementary metal-oxide semiconductor (CMOS) or low-voltage differential signaling (LVDS) interface, have been able to support on-chip decimation, showing that decimation is not strictly limited to >1GSPS RF sampling devices. The same benefits are available at these lower sample rates. In most cases, rather than using a parallel LVDS interface, you can use a serial LVDS interface with the addition of a frame clock on parallel LVDS devices to greatly reduce routing requirements when operating in decimation mode.

Fig 4: Typical receiver signal chainLastly, integrating the digital downconverter into the ADC removes external local oscillators, mixers and filters from the RF signal chain, all of which are required for downconverting signals to baseband before sampling in a traditional receiver signal chain, as shown in Figure 4.

As the ADC becomes more versatile in capturing data across different input bands, the importance of the front-end matching network grows, potentially requiring a wideband matching network. Dealing with the challenges of wideband matching networks introduces various trade-offs. For more details on input network matching, see “Unraveling the Practical Mysteries Behind RF Converter Front Ends.”


This installment explored decimation’s capabilities in RF sampling converters, from improving receiver efficiency by using multiband output to fast frequency hopping. Decimation proves crucial in high-bandwidth applications by reducing data rates and enhancing signal processing, paving the way for higher-performing RF systems. In the final installment of this series, I will discuss a practical application using the ADC32RF55 from Texas Instruments, illustrating the benefits of multiband output and the JESD204B interface.

Experienced Applications Engineer in the High Speed Data Converters group at Texas Instruments, with a Bachelor of Science in Electrical Engineering from The University of Texas at Dallas.

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