Imperas Announces the Latest Updates to RVVI & its Adoption by Leading RISC V Processor Developers

By Tiera Oliver

Associate Editor

Embedded Computing Design

July 12, 2022


Imperas Announces the Latest Updates to RVVI & its Adoption by Leading RISC V Processor Developers

Imperas Software Ltd announced the latest updates for RVVI (RISC-V Verification Interface) for RISC-V processor verification with virtual peripherals to support asynchronous events and system level interrupts.

Plus, the growing adoption of RVVI by many leading development teams that are driving the design innovations in RISC V processors. 

RVVI provides a common methodology for the key components of the testbench to connect the RISC-V processor RTL instruction trace and reference models to fully support the lock-step-compare co-simulation. The RVVIflexibility supports the full range of RISC-V specifications and features that can be adopted with increasing levels of complexity for designs with privilege modes, vector extensions, out-of-order pipelines, multi-threading, multi-hart, plus user-defined custom instructions, and extensions. RVVI supports the innovation of RISC-V with the flexibility required for verification IP and reuse as DV teams scale up to support the growth in RISC-V verification projects.

While RISC-V processor IP cores can be tested against the ISA (Instruction Set Architecture) specification, this is just the initial verification phase. The integration of the processor core must also be tested with the interactions across external peripherals and other system level components. By expanding the RVVI specification to include external components with a standards-based interface allows the reuse of components from the Open Virtual Platforms library of open-source models available at Testbenches with RVVIcompatible virtual peripherals can now be utilized to support RISC-V verification with system level testing of asynchronous interrupt and debug module events.

As a flexible framework, RVVI covers the needs of verification teams undertaking RISC-V processor functional verification and is a foundation for developing future guidelines, examples, and verification IP. For more experienced DV engineers, RVVI offers the flexibility to cover the most complex verification challenges for advanced RISC-V designs. Some early supporters of RVVI include Codasip, NSITEXE (Denso), OpenHW Group, MIPS Technology, Silicon Labs, and Valtrix Systems, plus many others yet to be made public.

The open standard RVVI (RISC-V Verification Interface) offers adaptability and verification IP reuse for the expanding community of developers undertaking processor verification, the open specification is available on GitHub at

The free riscvOVPsimPlus package, including the Imperas RISC-V Reference Model, latest test suites, and instruction coverage analysis, including updates for the latest RISC-V ratified specifications is now available on OVPworld at

The Imperas RISC-V processor verification technology already uses RVVI and is available now, more details are available at

Imperas will participate at Design Automation Conference 2022 (DAC 59), July 10-14 in San Francisco, California. Please stop by and see the latest trends and developments for RISC-V Verification at booth #2336 and at the OpenHW Pavilion booth #2340. For more details on all the presentations, talks, or to request a demo please visit


Tiera Oliver, Associate Editor for Embedded Computing Design, is responsible for web content edits, product news, and constructing stories. She also assists with newsletter updates as well as contributing and editing content for ECD podcasts and the ECD YouTube channel. Before working at ECD, Tiera graduated from Northern Arizona University where she received her B.S. in journalism and political science and worked as a news reporter for the university’s student led newspaper, The Lumberjack.

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