Siemens and UMC Develop 3D Integrated Circuit Hybrid-Bonding Workflow
October 11, 2022
Siemens Digital Industries Software and United Microelectronics (UMC) are collaborating to develop and execute a new multi-chip 3D integrated circuit (IC) planning, assembly validation, and parasitic extraction (PEX) workflow for UMC’s wafer-on-wafer and chip-on-wafer technologies.
The new hybrid-bonding 3D layout vs. schematic (LVS) verification and parasitic extraction workflow developed by UMC uses Siemens’ XPEDITION™ Substrate Integrator software for design planning and assembly. Siemens’ Calibre® 3DSTACK software for inter-die connectivity checking, Calibre nmDRC software, Calibre nmLVS software, and Calibre xACT™ software for IC and inter-die extended physical and circuit verification tasks also exist in the process.
In order to save space and attain more functionality for multiple devices on the same or smaller chip area, the process works by stacking silicon die or chiplets on top of one another in a single packaged device. The process is also designed to achieve lower power than traditional configurations of laying multiple chips on a PCB.
“We are pleased to be able to offer our customers a robust and proven foundry design kit and associate workflow that they can use to validate their stacked device designs, and help correct die alignment and connectivity, while extracting assembly parasitics for use in signal integrity simulations,” said Osbert Cheng, vice president of device technology development and design support at UMC. “Our mutual customers are increasingly interested in 3D IC solutions for applications including high-performance computing, RF, and AIoT, and this collaboration with Siemens can help to accelerate time-to-market of their integrated product designs.”
UMC plans to soon offer this new process to its global roster of customers.
For more information, visit: https://www.sw.siemens.com/en-US