The GENE-CML5 3.5" Subcompact Board From AAEON Offers Functionality to Support Industrial and AI Applications

By Tiera Oliver

Associate Editor

Embedded Computing Design

April 27, 2021


The GENE-CML5 3.5" Subcompact Board From AAEON Offers Functionality to Support Industrial and AI Applications

AAEON announced the GENE-CML5 3.5" subcompact board featuring the 10th Generation Intel Core processors (formerly Comet Lake).

The GENE-CML5 enables developers to deploy their next generation industrial and AI Edge applications.

The GENE-CML5 brings the LGA1200 socket 10th Generation Intel Core i3/i5/i7 processors, as well as Intel Pentium and Celeron processors to the 3.5" subcompact form factor. Supporting processors up to 4.4 GHz CPU frequency, the GENE-CML5 leverages the socket-type chipset to allow developers and end users to maintain, scale, and upgrade the platform to suit their processing requirements.

Combined with 64GB DDR4 memory, the GENE-CML5 delivers ideal processing speeds on par with desktop systems. Additionally, the chipset allows the compact board to take advantage of Intel vPro and Intel Active Management Technology (iAMT), enabling remote system monitoring and management.

The GENE-CML5 offers both flexibility and expandability to integrate into existing projects and bring the power of AI Edge Computing to any application. The board features a broad I/O layout including two USB3.2 Gen 2 ports, four USB2.0 ports, and dual Gigabit LAN ports. Display options include DP++, VGA, and LVDS connectors.

For expandability, the GENE-CML5 offers an M.2 2280 M-Key slot which can support AI expansion modules, as well as NVMe storage. Additionally, users have access to PCIe 3.0 [x4] expansion with FPC connector. Other storage options include two SATA III (6.0 Gbps) slots, allowing storage expansion.

The GENE-CML5 offers developers and users desktop performance in a compact form factor, suitable for deploying AI Edge applications where they're needed. With manufacturing support and OEM/ODM services from AAEON, developers can customize their boards including I/O layouts to suit their needs.

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Tiera Oliver, Associate Editor for Embedded Computing Design, is responsible for web content edits, product news, and constructing stories. She also assists with newsletter updates as well as contributing and editing content for ECD podcasts and the ECD YouTube channel. Before working at ECD, Tiera graduated from Northern Arizona University where she received her B.S. in journalism and political science and worked as a news reporter for the university’s student led newspaper, The Lumberjack.

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