A short time ago, Cortus released a pair of IP processor cores, the APS23 and APS25. The parts are based on the company’s v2 instruction set. The APS25 core is aimed at embedded systems that demand a high level of computational performance. Combined with the new instruction set, developers can maximize code density and extendability. The new instruction set allows the seamless mixing of 16-, 24- and 32-bit instructions without mode switching.

The low-power core is designed to support coprocessors or symmetric multiprocessing, and it can be used as a building block in a multicore system. The APS25 has a Harvard architecture, sixteen 32-bit registers, a five-stage pipeline, and a parallel multiplier. It supports the AXI4 bus as well as Cortus’ APS peripherals.

Up to eight co-processors can be added to an APS25 core. The coprocessor interface lets designers add custom coprocessors. Coprocessor instructions can be inserted into C-code appearing as function calls.

The APS23 is aimed at sensors, wearables, and other IoT applications. This low-power 32-bit core highlights efficiency, ease of integration, and cost of ownership for connected intelligent devices. It reduces system power by optimizing the size of the instruction memory. Potential targets include those that require always on/always listening modes and those with less demanding clock frequencies, such as Bluetooth Smart.

The APS23 has a Harvard architecture, sixteen 32-bit registers, a 3-stage pipeline, and a sequential multiplier. It delivers 2.83 DMIPS/MHz and 1.44 CoreMarks/MHz in computational performance. The minimal usable APS23 CPU starts around 9,800 gates when optimised for area. Dynamic power is 12 µW/MHz with a 90 nm process.

The APS tool chain and IDE (for C and C++) is available to licensees free of charge, and can be customised and branded for final customer use. Ports of various RTOSs are available such as FreeRTOS, Micrium µC/OSII.