ECOC 2019: eSilicon to Demonstrate 7nm 58G DSP-Based SerDes Over Seven-Meter and Five-Meter Samtec Cable Assemblies

September 20, 2019

Press Release

ECOC 2019: eSilicon to Demonstrate 7nm 58G DSP-Based SerDes Over Seven-Meter and Five-Meter Samtec Cable Assemblies

eSilicon and Samtec will demonstrate eSilicon?s 7nm 58G DSP-based PAM4/NRZ SerDes capabilities for two challenging data center applications.

eSilicon, a leading provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, and Samtec, a leading global manufacturer of electronic interconnect solutions, will demonstrate eSilicon’s 7nm 58G DSP-based PAM4/NRZ SerDes capabilities for two challenging data center applications including an industry-first use of a seven-meter cable assembly from Samtec.

What

eSilicon and Samtec have co-developed system-level solutions that emulate next-generation data center architectures for typical 19-inch rack-mount applications.

In the first application, eSilicon will demonstrate its SerDes operation over two 67cm AcceleRate® Slim Body Cable Assemblies and a five-meter (16-foot) ExaMAX® Backplane Cable Assembly providing mid-board to backplane communications via a cabled backplane architecture from Samtec. This demonstration highlights eSilicon’s SerDes architecture’s flexibility in supporting independent data rates and protocols on each individual lane, e.g., 50G PAM4 Ethernet, 24G NRZ CPRI and proprietary protocols up to 58Gb/s.

In the second application, eSilicon will demonstrate rack-to-rack communications using ExaMAX® Backplane Connector paddle cards and a seven-meter (23-foot) ExaMAX Backplane Cable Assembly. This demonstration shows the performance, robustness and extremely low power consumption of eSilicon’s 7nm 58G PAM4 and NRZ full-DSP long-reach SerDes in an extreme-use case featuring a total insertion loss of 45dB bump to bump.

A broad set of monitoring and diagnostic tools are available through eSilicon’s SerDes evaluation module kit and its graphical user interface to control, observe and analyze signal quality and performance metrics across the link in real time, including:

  • Bit error rate (BER) monitor
  • Eye diagram monitor
  • Equalization capabilities
  • Error histogram monitor with post-FEC estimator

Where & When

ECOC 2019
eSilicon Booth 650
September 23-25
Dublin, Ireland