Alliance Memory Expands Lineup of High-Speed CMOS DDR4 SDRAMs With New 8Gb Devices

By Tiera Oliver

Assistant Managing Editor

Embedded Computing Design

October 06, 2020

News

Alliance Memory Expands Lineup of High-Speed CMOS DDR4 SDRAMs With New 8Gb Devices

AS4C1G8D4 and AS4C512M16D4 High-Speed CMOS DDR4 SDRAMs

Alliance Memory announced that it has expanded its portfolio of higher-density CMOS DDR4 SDRAMs with two new 8Gb devices. The AS4C1G8D4 and AS4C512M16D4 offer low power consumption and ideal data transfer rates in 78-ball and 96-ball FBGA packages, according to the company.

Per the company, compared with DDR3 SDRAMs, the devices released reduce operating voltages from 1.65V to +1.2V (±0.06V) to increase battery life in portable electronics such as smartphones and tablets. For ideal efficiency and performance in 5G designs, desktop computers, and servers, the 1Gb x 8-bit AS4C1G8D4 and 512M x 16-bit AS4C512M16D4 offer up to 16 memory banks and deliver suitable clock speeds of 1333MHz for ideal transfer rates to 2666Mbps/pin.

With minimal die shrinks, the DDR4 SDRAMs provide suitable drop-in, pin-for-pin-compatible replacements for similar solutions, eliminating the need for redesigns and part requalification. Offered in commercial (0°C to +95°C) and industrial (-40°C to +95°C) temperature ranges, the devices are ideal for the industrial, networking, IoT, automotive, gaming, and consumer markets.

The AS4C1G8D4 and AS4C512M16D4 support sequential and interleave burst types with read or write burst lengths of BL8/BC4/BC4 or 8 on the fly. An auto pre-charge function provides a self-timed row pre-charge initiated at the end of the burst sequence. Refresh functions include auto- or self-refresh. RoHS-compliant, the devices are lead- (Pb) and halogen-free.

Samples and production quantities of the new 8Gb DDR4 SDRAMs are available now, with lead times of eight to 10 weeks. Pricing for U.S. delivery starts $8 per piece.

For more information, visit: https://www.alliancememory.com/

Tiera Oliver is the assistant managing editor at Embedded Computing Design. She is responsible for web content editing, product news, and story development. She also manages, edits, and develops content for ECD podcasts, including Embedded Insiders.

She utilizes her expertise in journalism and content management to oversee editorial content, coordinate with editors, and ensure high-quality output across web, print, and multimedia platforms. She manages diverse projects, assists in the production of digital magazines, and hosts company podcasts by conducting in-depth interviews with industry leaders to deliver engaging and insightful discussions.

Tiera attended Northern Arizona University, where she received her bachelor's in journalism and political science. She was also a news reporter for the student-led newspaper, The Lumberjack. 

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