Microchip Showcases PolarFire Devices for RISC-V and Space Compute Solutions

By Chad Cox

Production Editor

Embedded Computing Design

December 14, 2022


RISC-V Summit, San Jose. Microchip worked with NASA and the aerospace and defense industry to develop a RISC-V-based High-Performance Spaceflight Computing (HPSC) processor that is being presented at the RISC-V Summit. Microchip is also promoting its PolarFire 2 FPGA silicon platform and RISC-V-based processor subsystem with a software suite roadmap at the Summit.

The PolarFire 2 class is designed to enhance performance with an efficient power-curve adding RISC-V-based high-performance compute features. An included design tool set will diminish the task of understanding the complexities of the underlying FPGA hardware.

“Microchip was the first to offer FPGAs for power-efficient edge-compute segments, and the first to bring SoC FPGAs into volume production that support the RISC-V open Instruction Set Architecture,” said Shakeel Peera, vice president of marketing for Microchip’s FPGA business unit. Ideal applications for the PolarFire 2 are power-constrained systems in industrial imaging, robotics, AI-enabled medical systems, and smart defense and aerospace systems.

Peera continues, “At this year's summit, we are extremely excited to showcase our production ready PolarFire SoC family, partner ecosystem and solutions for today's power sensitive edge compute systems. An added bonus will be a sneak peak of where we are going next to deliver 15X more compute capability to our roadmap." 

RISC-V Summit attendees can see Microchip’s PolarFire family and Mi-V ecosystem, PolarFire 2 family and design tool suite preview, and HPSC offerings December 13-14, 2022, in Booth #PG5, Hall 2, at the San Jose McEnery Convention Center in San Jose, California. Attendees can learn more about Microchip during the following presentations at the conference:

  • “RISC-V Spotlight: Microchip’s RISC-V Journey to Deliver Innovation from Edge Compute to the Edge of the Solar System,” Bruce Weyer, corporate vice president, FPGA, Microchip, on December 13 in Hall 3 from 11:00 a.m. to 11:10 a.m.
  • “RISC-V Enabling High Performance Spaceflight Computing,” on December 14 in Hall 3 from 9:40 a.m. to 9:55 a.m.   

For more information on Microchip’s FPGA families click here.

Chad Cox. Production Editor, Embedded Computing Design, has responsibilities that include handling the news cycle, newsletters, social media, and advertising. Chad graduated from the University of Cincinnati with a B.A. in Cultural and Analytical Literature.

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