RISC-V Summit 2023: Embedded Editor Report

By Ken Briodagh

Senior Technology Editor

Embedded Computing Design

November 08, 2023


RISC-V Summit 2023: Embedded Editor Report

It’s been a banner day here at the Santa Clara Convention Center for the RISC-V Summit.

We’ve been treated to many amazing and optimistic keynotes, including one from Prahlad Venkatapuram, Senior Director of Engineering at Meta Platforms, who told us about how Meta us using RISC-V processers in its Data Center SoCs, and made a call to arms challenging RISC-V IP vendors to build to the growing needs of the data center.

BeagleBoardThere were several exciting industry announcements and news items today, too. Not least of which was that both  SiFive’s Performance P470 and BeagleBoard.org's BeagleV-Fire have been awarded Best in Show from Embedded Computing Design’s own editorial staff.SiFive

In terms of industry news, Synopsys has announced that its ARC processor IP line now includes a RISC_V tailored IP: the ARC-V The company said that the new ARC-V Processor IP is built on the microarchitecture of its existing ARC Processors, but now can also leverage the growing RISC-V software ecosystem for customers. “This is not our first foray into the software IP business, but if we don’t provide a software ecosystem, we’re not going to be successful,” said Matt Guttierrez, Senior Director of Product Management for Synopsys’ portfolio of processor and security IP and tool solutions. “We see that with ARC and we’re seeing it with RISC-V.”

Also today, Semidynamics announced the launch of its first fully-coherent RISC-V Tensor unit that the company says will not only reduce latency, processor cycles and energy use, it will also, when married to the Vector regulators, solve the memory wall problem. Roger Espasa, CEO & Founder at Semidynamics Technology Services, said the full system is designed to be ideal for AI and machine learning embedded systems, thanks to the new Tensor unit, and the company’s customizable 64-bit cores, married to the vector regulators, Gazzillion data management software, and the unique architecture that brings all these units together in one piece.

There’s more to know about these news items, to be sure, but that’s enough for now.  

We met with amazing companies across the RISC-V world from Axcelera AI, which specializes in computer vision AI via RISC-V, to CAST, offering RISC-V IP cores for ASICs and FPGAs. We met with Siemens and learned about its focus on virtualization and emulation software solutions, and touched on the Memory Wall with Arteris IP and how it needs to be solved with architecture.

There was lots more, and even more to come tomorrow, so watch this space!

Click here for Part Two.

Ken Briodagh is a writer and editor with two decades of experience under his belt. He is in love with technology and if he had his druthers, he would beta test everything from shoe phones to flying cars. In previous lives, he’s been a short order cook, telemarketer, medical supply technician, mover of the bodies at a funeral home, pirate, poet, partial alliterist, parent, partner and pretender to various thrones. Most of his exploits are either exaggerated or blatantly false.

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