The Road to RISC-V Summit: CAST to Highlight 32-bit Solutions in Functional Safety and Ultra-Low Power

October 18, 2024

Blog

During this year’s RISC-V Summit, CAST will be in booth S13 demonstrating its processors offered in ASICs or FPGAs for embedded systems, Internet of Things edge devices, industrial control systems, automotive, and aerospace applications. CAST’s RISC-V IP core line features processors focused on competitive 32-bit solutions in Functional Safety and Ultra-Low Power.

The EMSA5-FS 32-bit Embedded RISC-V Functional Safety Processor is an ISO26262 ASIL D Ready IP core that offers:

• Single-issue, in-order, 5-stage pipeline processor with an optional L0 instruction cache
• Extensive RV32 base integer or base embedded ISA options, including full, partial, or optional support for RV32[I/E][C][M][F][D][A][Zicsr][Zifencei] and Vector Instructions
• Fail-safe design features, including Dual Modular
• Redundancy (DMR) in Lockstep or triple (TMR), Error Correcting Code (ECC), and sample Reset and Safety Manager modules
• A complete ISO 26262 Certification Package, including a Safety Manual (SAM) and a Failure Modes, Effects and Diagnostics Analysis (FMEDA) document

The performance and resource requirements of the EMSA5-FS vary with its configuration and ASIC or FPGA implementation. DMR versions start at 40k gates, and TMR at 60k. EMSA5-FS performance can surpass frequencies over 1GHz on advanced processor nodes.

CAST’s 32-bit RISC-V low-power processors for embedded applications require a small silicon footprint for minimal leakage and dynamic CPU power. They also employ advanced power management techniques such as dynamic clock gating and clock frequency scaling. RISC-V support includes RV32 base integer or base embedded ISA and extensions, including full, partial, or optional support for RV32[I/E][C][M][F][D][A][N][Zicsr][Zifencei] and Vector Instructions.

For more information, visit cast-inc.com/processors/risc-v.