Lattice Secure Control FPGA Now NIST Certified
October 17, 2019
MachXO3D secure system control FPGAs combine a secure, dual-boot configuration block with 9K LUTs to simplify establishing a hardware root of trust.
Lattice Semiconductor’s MachXO3D FPGAs have been certified under NIST’s Cryptographic Algorithm Validation Program (CAVP), which validates that the devices’ cryptographic algorithms comply with Federal Information Processing Standards (FIPS).
MachXO3D secure system control FPGAs combine a secure, dual-boot configuration block with 9K LUTs to simplify establishing a hardware root of trust. Other device highlights include:
- Embedded security block provides pre-verified support for cryptographic functions such as ECDSA256, ECIES, AES, SHA, HMAC, TRNG, Unique Secure ID, and public/private key generation
- Secure configuration engine that only accepts FPGA configurations from trusted sources
- Dual on-device configuration memories for fail-safe reprogramming of firmware
- Up to 2700 Kb of Flash memory
- Up to 430 Kb sysMEM embedded block RAM
- Up to 383 I/Os (configurable to support LVCMOS 3.3 to 1.0)
Compliance with the NIST Platform Firmware Resilience specification and now CAVP affirms that MachX03D FPGAs are capable of detecting and preventing systems from unauthorized firmware accesses throughout their operational lifecycles, and also allowing them to recover safely.
For more information on the MachXO3D, visit www.latticesemi.com/MachXO3D.
For more on the MachXO3D’s CAVP certification, visit csrc.nist.gov/projects/cryptographic-algorithm-validation-program/details?validation=31395.