Reduce DFT Footprints in ASIC Design by Addressing Test Time
October 22, 2020
An Approach Using Test Channel Reduction to save Testing Cost
Since the past decade, different application areas starting from consumer applications, networking, or defense systems, including sensors, are the influence of semiconductor VLSI circuit technology. For a ASICs (SoC) power, performance (time), and area are always challenging factors in designing. Based on the user application, optimization on one or all of the above factors used to be done. Apart from PPA, dealing with IC structural test -DFT time also becomes an aggregative challenging task. As design complexity is increasing multi fold day by day – thanks to Moore’s law, using conventional DFT scan methodology ASICs can be tested but it results in higher test data volume and test time increases non-linearly. Earlier, testing cost was the only factor considered while implementing scan compression. The key requirement of any compression technology is preserving the high-test quality compared to standard (uncompressed). Test Compression ratio plays a vital role in reducing total test time. In this paper, we mainly focus on an approach towards test time reduction using optimum number of test channels at chip top without compromising test quality.
ASICs, as defined by the name, are designed for specific applications. Different technologies can be used to create ASICs but CMOS is common due to high reliability and low cost. For ASICs (SoC design) power, performance (time), and area are challenging factors in designing. Based on application weightage of these factors depend on ASIC. Here, Fig.1 shows different applications and Table I lists weightage of factor.
Fig. 1 ASIC Applications
Power, Area & Time comparison
II. Need of Scan Compression in ASIC Design
Earlier, tester cost was the only factor considered while implementing scan compression. Number of test patterns depends on test data volume and test time. Option of pattern truncation results in lower test coverage and ultimately an increase in defective parts per million (DPM) that are shipped to customers, which affect yield . Therefore, in order to avoid an increase in test escapes due to low-test quality, the industry has recognized an inevitable need for test pattern compression. Next-Gen ASIC (SoC) design flow has more complex structure which leads to have new fault models and additional test patterns to detect those and compression helps with that factor as well .
Result of Scan Compression is as follow :
• Reduce the requirement of scan data memory
• Reduce test application time per part
• Reduce the number of required scan channels
• Reduce simulation time for serial load patterns
A. Introduction to Compression Technology
The key requirement of any compression technology is preservation of high test quality when compared to standard (uncompressed) ATPG. Compression technology is based on traditional, deterministic ATPG and uses the same fault models to obtain similar test coverage using a familiar flow . It extends ATPG with improved compression of scan test data and a reduction in test time. It achieves compression of scan test data by controlling a large number of internal scan chains using a small number of scan channels .
B. Basic Compression Terminology
For Compression, the external scan chains are called scan channels to distinguish them from the internal scan chains inside the core . Their number is significantly less than the number of internal scan chains. Determination of chain to channel ratio, defines the compression of the design, which directly affects the test coverage and test data volume. An effective compression depends on the Scan chain and scan channel .
Compression can be expressed as a ratio of the Tester Memory of ATPG vs. Compression or as a ratio of the no. of test cycles of ATPG vs. Compression. Since the no. of channels is the same, both calculations will be equivalent .
The compression is a function of two factors . :
* Chain-to-channel ratio: The ratio of scan chains (internal to the core) to scan channels (external)
* Change in the number of shift cycles for each pattern (no. of scan chains, no. of scan cells, and initial cycles per pattern).
III. Scan Compression Analysis
We only have direct control of the chain-to-channel ratio. The three factors are, however, related. The higher the ratio of internal scan chains to external scan channels, the higher the compression per pattern but compression analysis will give you an estimate calculation of compression as you vary the different factors .
A. What is Analyzing compression?
Usually the number of scan channels are dictated by hardware resources such as test channels on the ATE and the top-level design pins available for test. However, for effective compression we can change the scan chain requirement. . The compression analysis command works on the effects of different chain to channel ratios on test data without making modifications to your chip design. Compression analysis helps to decide chain to channel ratios, test coverage, and test data volume for compression structure.
B. How Compression analysis works?
It analyzes the compression for an application in two steps.
The two steps are as follows:
1. Analyzes a scan-inserted design and gives a range of maximum chain to channel ratios where the test coverage begins to decline.
2. Calculates a hardware configuration for a specified chain to channel ratio, generates temporary test patterns, and returns test data statistics for the compression configuration .
C. Flow for Compression Analysis:
1. Check the current scan configuration and calculate channel/chain ratio.
a. Based on compression configuration it will give you estimated compression ratio. (Check with intest/extest configuration report).
2. Write out scan design netlist with existing scan configuration and run pattern generation.
3. Before pattern generation starts add analyze_compression command. (Before pattern generation) .
4. This command will help analyzing compression and give you following statistics at end of pattern generation phase.
- The tool analyses the design and returns a range of chain to channel ratio values beginning with the ratio where a negligible drop in fault coverage occurs and ending with the ratio where a 1% drop in fault coverage occurs as follows:
Fig. 2 Data for Compression Analysis 
6. Pick the corresponding channel to chain ratio value for negligible fault coverage drop and re-calculate channel number.
7. Updated channel number will be the minimum channel required to achieve high compression with negligible fault coverage drop.
Based on Flow, channel reduction experiment were performed and Table II shows result comparison with respect to channel to chain ratio, compression ratio, and coverage and pattern number.
IV. Effect On Hierarchical Test
Working on cutting edge technology leads to low pin count for ASIC/SoC at top level. Limited pins will be available at top level for testing, most of the time these pins are shared between functional pins . Number of pins are restricted at top level. Using following example we can check that how block level scan channel reduction helps during chip level collaboration. Consider scenario shown in figure below.
Using different cases/scenarios we will check how scan channel reduction helps at top level.
1) Case 1: Consider scenario that we have 3 block cores available and having two instances available at chip top level. Each core runs through 4 scan channels shown in fig 3(a). During chip top level pattern generation and simulation all the three instance will be used in group. 3 core/block * 2 instance = 6 instances at top level. Consider we will be having 12 channels available. To accommodate all 6 instances we need to create 2 mode for pattern generation as shown in fig 3(b).
Fig 3(a). Flat Compression At Core 
Fig 3(b). Conceptual drawing for Hierarchical Test
So in this scenario we need to create total 2 groups to accommodate all instances (3 each) to use 12 scan channels available. Now let's see another case.
2) Case2: In this case consider using analyze_compression. We have done scan channel reduction and the number of scan input/output channels used are 2 for each core as shown in figure 4(a). Lets check statistics. 3 core blocks * 2 instances = 6 instances , Total scan channel available at top are 12. Each blocks will use only 2 channels , so total channels used are 6 channels. Considering this now we can accommodate all 6 instance in 1 mode as shown in fig 4(b). Test time will be reduced by half.
Fig 4(a). Flat Compression At Core 
Fig 4(b). Conceptual drawing for Hierarchical Test
V. Trade-off between increased Compression and pattern inflation
1) Compression ratio
Reduction in scan channel numbers leads to higher compression ratio. It is also important to balance the compression target with the testing resources and design needs. Using an unnecessarily large compression target may have an adverse effect on compression, testing quality, and chip design layout.
2) Lower Test Coverage
Higher compression ratio increases the compression per test pattern but also increases the possibility of generating test patterns that cannot be compressed and can lead to lower test coverage .
3) Pattern Inflation
Higher compression ratios also decreases the number of faults that dynamic compaction can fit into a test pattern. This can increase the total number of test patterns to detect those faults.
To mitigate the effect of higher compression on ATPG coverage and pattern number, during analyze_compression, choose the value of channel to the chain ratio for the negligible effect on coverage.
In this paper, we checked that scan compression indeed helped in reducing the testing time (DFT) in ASIC design, but also scan channel reduction is a way of helping the test time at top level. According to the example case study, we can determine the minimum number of channels required for effective compression and also how it’s affecting other parameters like chain to channel ratio, compression ratio, and test time. Nowadays in the semiconductor industry, these factors are widely used to save the testing cost.
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Chintan Panchal works as a Delivery Manager (Level 1) in ASIC division, at eInfochips, an Arrow company. He has more than 18 years of experience in ASIC DFT. He has experience of working on various technology nodes, from 180nm to 7nm, handling different DFT tasks, and manages a team of engineers.
Charu Patel works as Senior Engineer in the DFT at eInfochips, an Arrow company. She has more than three years of experience in ASIC DFT, which includes working on various technology nodes, from 28nm to 7nm, handling block level and top level DFT activities.