New CORE-V CVA6 Platform Project Announced at RISC-V Summit

By Chad Cox

Production Editor

Embedded Computing Design

November 09, 2023


New CORE-V CVA6 Platform Project Announced at RISC-V Summit
Image Credit: OpenHW Group

Santa Clara, California. OpenHW Group publicized its CORE-V CVA6 Platform project, an open-source FPGA-based software design and test environment for RISC-V processors. The muli-member project will deliver client and server-compliant open-source processor designs utilizing the CV-Mesh clustering Network-on-Chip (NoC).

Coherent scaling for hundreds of CVA6 cores is possible and aids in the acceleration of integration and testing of differing CVA6 platform configurations. An important aspect of the platform is the ability to upgrade when new technologies are discovered, but also keeping RISC-V ISA Specifications up to date.

According to OpenHW Group, the CVA6 Platform implementation using FPGA-based hardware emulation, provides fsystem level silicon logic equivalence as opposed to an interpreted software simulator.

Initial Availability

  • The CVA6 Platform on Amazon AWS EC2 F1 instances will enable SW testing on the octal CVA6 cluster in the cloud
  • Digilent Genesys 2 and Nexys Video boards provide a low-cost entry point for basic testing with 1-2 CVA6 cores in a bench top environment
  • Other configurations such as: Xilinx VC707 boards which can support 1-4 CVA6 cores; Xilinx VCU118 and BittWare XUPP3R boards which can support around 8-10 CVA6 cores; and Xilinx Alveo U200 and U250 boards which can support significantly more CVA6 cores (~15) to enable testing of larger parallel/distributed software on many core systems are also being considered as part of the project.

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Chad Cox. Production Editor, Embedded Computing Design, has responsibilities that include handling the news cycle, newsletters, social media, and advertising. Chad graduated from the University of Cincinnati with a B.A. in Cultural and Analytical Literature.

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