RISC-V International Ratifies 15 New Specifications
December 06, 2021
RISC-V members ratified the Vector, Scalar Cryptography, and Hypervisor specifications, which will help unlock new opportunities for developers creating RISC-V applications for artificial intelligence (AI) and machine learning (ML), the Internet of Things (IoT), connected and autonomous cars, data centers, and beyond.
RISC-V International's 15 newly ratified specifications represent more than 40 extensions for the free and open RISC-V instruction set architecture (ISA).
The RISC-V Vector specification will help accelerate the computation of data intensive operations like ML inference for audio, vision, and voice processing. With RISC-V Vector, developers can process complex data arrays and scalar operations quickly and with low latency. The simplicity and flexibility of Vector allows companies to customize RISC-V solutions for a wide variety of edge computing applications from consumer IoT devices to industrial ML applications.
“The new RISC-V Vector specification will change the way people think about vector designs,” said Dave Ditzel, Founder and Executive Chairman of Esperanto Technologies. “With just over 100 instructions, the extension offers a simple and elegant approach to efficiently process the latest machine learning algorithms.”
The RISC-V Hypervisor specification virtualizes supervisor-level architecture to efficiently host guest operating systems atop a type-1 or type-2 hypervisor. Virtual machine implementations require the RISC-V Hypervisor specification. The Hypervisor specification will help drive RISC-V adoption in cloud and embedded applications where virtualization is critical, such as in data centers, automotive applications, and industrial control applications. The RISC-V community has ported KVM and other open source Virtual Machines on top of simulators using the new specification.
The RISC-V Scalar Cryptography specification enables the acceleration of cryptographic workloads for small footprint deployments. These extensions significantly lower the barrier to entry for secure and efficient accelerated cryptography in IoT and embedded devices.
“The RISC-V Scalar Cryptography extensions allow for implementing standard cryptographic hash and block cipher algorithms that are an order of magnitude faster than using standard instructions in some cases. With RISC-V’s transparent and open approach, anyone can efficiently implement critical cryptographic algorithms in any class of CPU,” said Ben Marshall, Cryptographic Hardware Engineer at PQShield and member of the RISC-V Technical Steering Committee. “In addition to the performance benefits, these new extensions are very cheap to implement so companies can integrate popular cryptography algorithms in even the smallest connected devices.”
Krste Asanović, Chair of the RISC-V International Board of Directors, said, “The development of these specifications really showcased the incredible benefits of open collaboration across companies and geographies as members worked together to develop novel approaches for the latest computing requirements.”
For more information, visit Risc-V International.