Spirent and Cadence Collaborate to Bring Advanced Chipset Testing to Pre-Silicon Verification

By Tiera Oliver

Associate Editor

Embedded Computing Design

October 31, 2023


Spirent and Cadence Collaborate to Bring Advanced Chipset Testing to Pre-Silicon Verification

CALABASAS, CA. – Spirent Communications plc announced a collaboration with Cadence Design Systems, Inc., to deliver a joint networking system-on-chip (SoC) verification solution that bridges to link the divide between pre-silicon and post-silicon verification.

The collaboration provides brings Ethernet traffic emulation and testing capabilities to pre-silicon verification in the Cadence Palladium Z2 Enterprise Emulation and Protium X2 Enterprise Prototyping systems. The solution is also designed to emulate any port speed from 1G to 800G at the application level, and introduce additional features to enable new use cases they arise.

The solution is jointly developed by Spirent and Cadence, and designed to enable the increasing data bandwidths needed to verify designs for data centers and other high-performance applications. The partnership combines the data rates and port densities of Spirent TestCenter with the verification capabilities of the Cadence Palladium and Protium systems as a unified solution with reusable, portable, automated test cases.

Benefits of the joint solution include:

  • Effective, efficient testing for pre-silicon validation from 1G to 800G for application-level testing;
  • Comprehensive integration of the test application and emulation environment without the need for external test hardware;
  • Cost savings from identifying and fixing issues in early-stage chip design;
  • A unified test platform that bridges gaps between pre- and post-silicon verification, enabling continuity of testing from the earliest phases of product development through customer deployment;
  • Capability to test all phases of silicon product lifecycle, time-saving application re-utilization, implementation of standard metrics for more effective measurement and result analysis, and integration into CI/CD workflows.

Michael Young, senior product management group director, System and Verification Group at Cadence said: “When integrated into the Palladium emulation and Protium prototyping systems, Spirent’s’ Ethernet traffic emulation and test capabilities allow mutual customers to extend their verification with real-world traffic and scenarios, greatly reducing time to market.”

For more information visit: www.spirent.com/campaign/accelerate-chipset-design-and-development-with-cadence, and view this short video and download the Spirent Chip Design Verification Solution datasheet.

Tiera Oliver, Associate Editor for Embedded Computing Design, is responsible for web content edits, product news, and constructing stories. She also assists with newsletter updates as well as contributing and editing content for ECD podcasts and the ECD YouTube channel. Before working at ECD, Tiera graduated from Northern Arizona University where she received her B.S. in journalism and political science and worked as a news reporter for the university’s student led newspaper, The Lumberjack.

More from Tiera