Embedded Computing Design

Oxford, United Kingdom. Imperas Software Ltd. revised its ImperasDV for maintaining the expansion of RISC-V verification supporting both RTL bug detection and analysis while collaborating with design flow implementation in EDA SystemVerilog environments with Cadence, Siemens EDA, and Synopsys. Imperas leverages RISC-V for its ability to be customized for specific industry needs. “RISC-V offers new freedoms in design flexibility which is driving a new wave of innovation across the semiconductor industry in almost all market segments,” said Larry Lapides, VP of Sales at Imperas Software Ltd.

Edgar Allan Poe once penned, "Travelling is like dreaming: the only difference is that not everyone, once awaken, can recall their dream. Whereas, everyone has a vivid memory of the trip from which he has returned. " With this in mind, let’s continue our travels on the road to embedded world 2023.

Chicago. Newark will commit itself to STEM education by providing kits to students and their professors to enjoy and learn from hands-on experiences. Educators can collaborate with Newark by constructing a custom kit for students including customized classroom kits and developing single board computers. Cliff Ortmeyer, Global Head of Technical Marketing at Newark stated, “We want to encourage everyone to stretch their minds and think creatively and strategically, this starts when students are young and in the classroom.”

Monheim am Rhein, Germany. For the possibility to see and operate an integrated system vis USB, SEGGER announced its emVNC-Server (Virtual Network Computing). The general use of USB allows for the emVNC-Server to be integrated simply by connecting into an active interface opening it up to an abundance of options.

Milwaukee, Wisconsin. Review Display Systems (RDS) released its 10.1-inch IPS TFT LCD smart display module, the DMG10600T101-33WTC, leveraging a Rockchip RK3288 ARM-based System on Chip (SoC) and utilizing a 32-bit Cortex A-17 core operating on Android OS.

RISC-V Summit, San Jose. during the RISC-V Summit 2022, StarFive Technology’s Director of Software Engineering, Chin Liang, presented on StarFice's work toward developing the next generation of the RISC-V ecosystem. In Liang’s lecture, you will learn in-depth knowledge of RISC-V architecture, tools, and Linux distribution. See how you can use the knowedge gained for solutions in your designs.

RISC-V Summit, San Jose. Ventana Micro Systems Inc.’s founder and CEO Balaji Baktha will present Ventana’s Veyron family at his RISC-V Summit keynote address. The standards based Veyron V1 is a RISC-V processor that will come in chiplets and IP assisting in single thread performance targeting solutions for data centers, automotive, 5G, AI, and client applications.

Uppsala and Gothenburg, Sweden. IAR Systems and Gaisler are partnering on an IAR Embedded Workbench for RISC-V (IAR I-jet), a comprehensive development toolchain assisting engineers with an abundance of resources tied into one simplistic development platform. The workbench includes many debugging and assessment protocols for code and data breakpoints, as well as runtime stack analysis, call stack visualization, and code coverage analysis. The IAR I-jet is an economical debug interface with the Noel-V processor from Gaisler.

As objects exit Earth’s atmosphere, radiation levels become increasingly destructive to both organic and inorganic materials. The latter includes electronics, which are susceptible to Gamma rays, X-rays, and other high-energy particles that can cause single event upsets (SEUs, also known as bitflips) in memory, voltage spikes in analog circuitry, and other faults that can crash programs or entire systems.

RISC-V Summit, San Jose. Solid Sands will be announcing it has been invited to the RISC-V community as a strategic member at the RISC-V Summit. While attending the show, industry insiders will learn Solid Sands expertise on how to qualify C and C++ standard libraries for safety-critical applications.

RISC-V Summit, San Jose. Microchip worked with NASA and the aerospace and defense industry to develop a RISC-V-based High-Performance Spaceflight Computing (HPSC) processor that is being presented at the RISC-V Summit. Microchip is also promoting its PolarFire 2 FPGA silicon platform and RISC-V-based processor subsystem with a software suite roadmap at the Summit.

RISC-V Summit, San Jose. Ashling is showcasing its Vitra-XS, a debug and trace probe for integrated design with support for RISC-V and Arm platforms. Ashling developed the Vitra-XS to collaborate with Ashling’s RiscFree Eclipse based IDE & Debugger utilizing USB 3.0, 38-way Mictor target connector, 512 MB of on-board trace storage, RISC-V debug & trace standards E-Trace and N-Trace, and Arm CoreSight debug & trace standards SWD, DAP, ETM, PTM, STM, and CTI.

RISC-V Summit, San Jose. Imperas Software Ltd., announced that Imagination Technologies will utilize the Imperas model IMG RTXM-2200, from Imagination’s RISC-V Catapult family, as a solution for software design in virtual platforms and EDA environments. The IMG RTXM-2200 is a scalable real time deterministic 32 bit embedded CPU developed for commercially available components.

 

RISC-V Summit, San Jose. Siemens Digital Industries Software announced that its security and cloud enabled Sokol Flex OS software, centered around the open-source Yocto Project industry standard, supports RISC-V embedded advancement with its customizable Linux platforms for the RISC-V architecture. “Siemens continues to show leadership within the RISC-V ecosystem with the launch of Sokol Flex OS for RISC-V,” said Krishnakumar Ramamoorthi, senior product marketing manager of Microchip Technology's FPGA business unit.

RISC-V Summit, San Jose. MIPS has designated Imperas to deliver flexible framework RISC-V processor verification tools to simplistically adapt from issue recognition and debug resolution in a testbench ecosystem consistent with the SystemVerilog EDA tools. The provided tools support the open standard RVVI (RISC-V Verification Interface) with the ability to communicate with a processor.

RISC-V Summit, San Jose. Codasip announced its SecuRISC5 for reliable custom compute that utilizes reference designs merging Codasip IP and third-party technology. The recently launched Codasip Labs¹ will recognize openings where SecuRISC5 will be attentive, a hub, and a coordinator of pan-industry collaboration.

ECD is once again back on the Road to embedded world with our blog series. We are packing up and starting at the Atlantic with ARM, headquartered in Cambridge, England, right on the River Cam. ARM will be showcasing Cloud-native application development, IoT, and Automotive use cases. Visit Stand 4 - 540 to see how ARM takes the heavy lifting out of your Industrial needs. So, grab some coffee, buckle up, and put on some tunes, this is going to be a fun ride.

CUPERTINO, Calif. Ventana Micro Systems Inc. released its standards-based data center class of RISC-V computing, the Veyron V1. The Veyron V1 is a member of Ventana’s Veyron family of high-performing RISC-V processors. According to Ventana, Founder and CEO Balaji Baktha will speak on the many features of the Veyron family during his RISC-V Summit keynote. Highlights are expected to include, an eight wide and aggressive out-of-order pipeline, 3.6GHz, 5nm process technology, 16 cores per cluster, high core count multi-cluster scalability up to 128 cores, and 48MB of shared L3 cache per cluster. 

Geneva. STMicroelectronics updated its X-CUBE-TCPP software pack with improvements to its portfolio of USB Type-C port-protection ICs and STM32 interface ICs operating from 5V/0.5A up to 48V/5A (240-Watt) within ratification 3.1. The specification provides libraries for three USB Type-C port-protection ICs in ST’s portfolio, the TCPP01-M12 for sink applications, the TCPP02-M18 for source applications, and the TCPP03-M20 for dual-role power (DRP) applications.

San Diego, CA. congatec applauds the approval of the COM Express 3.1 standard and launched 10 compliant Computer-on-Modules powered by 12th Gen Intel Core processors (formerly codenamed Alder Lake). Included in the ratification is a revised 16 Gbps COM Express connector supporting high-speed interfaces like PCIe 4.0 and USB 3.2.